As the demands for video signal processing increase, there may be a desire for digital signal synthesis and high accuracy DACs at high clock frequencies and with wide dynamic ranges. Complementary metal-oxide-semiconductor (CMOS) current-steering DAC architectures may provide a desirable structure for most of these applications. The current-steering DAC may have the advantages of small resolution below 10 bits and being very fast. Another good property of the current-steering DAC may be high power efficiency since all power is directed to the output. The current-steering may be suitable for high speed, high resolution applications, especially when special care is taken to improve the device mismatching, glitches, and current source output impedance for high bit converters. The current sources may be typically implemented with cascaded NMOS or PMOS transistors.
FIG. 1 illustrates a typical current-steering DAC with current source. A current steering DAC includes a plurality of unit current cells 101 corresponding to the number of bits of a digital input signal, and a bias circuit for generating a bias voltage for adjusting current values of the unit current cells to a prescribed value. When a digital input signal is applied to the current steering DAC, the current steering DAC may select currents to be applied from the plurality of unit current cell and outputs the current through its respective switch. When the switch is “ON,” the current flows through ROUT 102 and when it is “OFF,” the current is bypassed to ground. Finally, the sum of the selected currents is sent out from the analog output terminal 102. The node 103 is the point where all the currents contributing to the output sum up to flow through ROUT, and the node 104 is the point where all the current which is bypassed to ground adds up. A potential advantage with this architecture is that almost all the current passes through the output, making this architecture power efficient. Therefore, this type of converters may be better for high speed D/A converters.
FIG. 2 illustrates an internal architecture of a unit current cell of the current-steering DAC. M1 (PMOS transistor) acts as a current source, which is controlled by bias voltage (Vbias). Another bias source node_int provides a fixed current to the cascode inputs. M2 (PMOS transistor), M5 (MOS transistor), and M6 (NMOS transistor) are the part of a regulated cascode, which are basically used to reduce the drain-source voltage (Vds) variation across the current source M1, so that the current and impedance variation may be minimized. M3 and M4 are the switches, which provide the path to the current either ROUT or ground (GND) depending upon the input control signals. Since the circuit is a feedback circuit, Capacitor C1 is acting as a compensation capacitor to ensure the stability of the system.
Conventionally, in a DAC, the output voltage is proportional to the data code at the input, but an increase in the voltage across the output load for a data code of high value may eventually push the switch into a linear mode from a saturation mode, thereby degrading the output impedance (Zout) and bringing down the Total Harmonic Distortion (THD) to a low level. Moreover, in nano/micro dimension integrated chips, it may become even more difficult to keep the source and the cascode in saturation mode due to reduction in supply voltages because of reduced size.
Further, due to supply limitation switch sizes becoming large, which again decreases the Zout due to increased parasitic capacitance and thereby reducing THD, a current source M1 along with active cascode stage M2, M5 and M6 may be used with a very small series switch M3 and M4 with the purpose to achieve high output impedance and thus the high THD. However, when the sizes of the switches M3 and M4 are reduced, the voltage drop across the switch may become significant and impact the circuit. The switch M3 may be generally in the saturation mode at low output voltage (Lower Data Code), and may be in a linear mode at higher output voltages (Higher Data Code). This may create a capacitance variation at the output as the drain-source resistance Rds of the switch M3 decreases when it is in the linear mode, making the capacitance of the drain of M2 visible at the output. As the switch M3 is in series with the cascade so in order to achieve a cascade in saturation mode, it may become necessary to increase the size of the cascade, which makes the variation of capacitance even larger, thereby degrading the linearity of the DAC. Furthermore, due to dynamic range limitation, it may become difficult to implement multiple cascades.